1. Field of the Invention
The present invention relates to the field of computer systems; more particularly, the present invention relates to a method and apparatus for providing inter-operability of different Peripheral Component Interconnect (PCI) building blocks, such as a host bridge to connect a Central Processing Unit (CPU) and memory subsystem to a PCT bus and an expansion bus bridge to connect an Industry Standard Architecture (ISA) bus or an Extended Industry Standard Architecture (EISA) bus to the PCI bus.
2. Description of Related Art
A Peripheral Component Interconnect (PCI) bus is a high speed Input/Output (I/O) bus for a computer system. The PCI signals and specifications are defined in the PCI specifications version 2.0 or above. The PCI specifications are endorsed by an industry organization of which Intel Corporation of Santa Clara, Calif. is a member. The PCI bus is coupled to a CPU and memory through a host bridge. A Small Computer System Interface (SCSI) host adapter may be coupled to the PCI bus to interface to devices such as disk drives, tape drives, and Compact Disk-Read Only Memory (CD-ROM). In addition, a graphics adapter may be coupled to the PCI bus to interface to video frame buffers and a local-area network (LAN) adapter may be coupled to the PCI bus to interface to a LAN.
The PCI bus is also coupled to an expansion bus through an expansion bus bridge. The expansion bus may be an Industry Standard Architecture (ISA) bus or an Extended Industry Standard Architecture (EISA) bus. Devices connected to the expansion bus may include bus masters which generate and respond to requests from other devices (either from the expansion bus or the PCI bus) and slaves such as memory and I/O devices that only respond to requests from other devices.
The host bridge contains an arbiter for the PCI bus which uses an algorithm to determine which bus master is granted control of the PCI bus when multiple bus Masters have requested use of the PCI bus. The arbiter asserts a signal corresponding to the bus master which is granted access to the PCI bus.
The host bridge, expansion bus bridge, and other devices on the PCI bus may have write buffers to improve performance according to well-known methods. A posted write buffer for the host bridge, for example, would post data received from the memory or CPU in a buffer and indicate that the data has been transferred. This allows the memory or CPU to proceed to subsequent operations while the host bridge waits for access to the PCI bus to perform the necessary operation to the target device. A posted write buffer for the expansion bus bridge stores information directed to the expansion bus and information directed to the PCI bus.
In order to maintain memory coherency and prevent deadlocks (e.g. where two or more bus masters require access to the bus before the other can proceed), a flush of some or all of the posted write buffers may be necessary before proceeding with another request according to well-known methods. When a flush is requested, valid writes in the posted write buffer are written to the target device and invalidated in the posted write buffer before a subsequent operation is performed. In some cases, only those writes directed towards the PCI bus and not to the EISA bus are flushed. In other cases, writes directed towards the EISA bus are flushed through the PCI bus.
In the following description, conventional symbols for signal names are used. For example, the symbol "#" indicates an active LOW signal. The expansion bus bridge performs arbitration and buffer management for the use of the PCI bus to the host bridge using five signals: (1) a PCI bus request (REQ#) signal which indicates that a bus master is requesting access to the PCI bus, (2) a PCI bus grant (GNT#) signal which indicates that the arbiter has granted access to that bus master, (3) a flush request (FLSHREQ#) signal which initiates a flush of the posted write buffers containing valid writes directed towards the PCI bus and then temporarily disables the posted write buffers, (4) a memory request (MEMREQ#) signal which initiates a flush of the posted write buffers containing valid writes directed towards the memory and temporarily disables the posted write buffers, (5) and a memory acknowledge (MEMACK#) signal that indicates that the posted write buffer flush corresponding to either the FLSHREQ# signal or the MEMREQ# signal is completed.
The prior art host bridge manufactured by Intel Corporation of Santa Clara, Calif., incorporates a two signal arbitration and buffer management control scheme including a PCI Hold (PHLD#) signal and a PCI Hold Acknowledge (PHLDA#) signal. The PHLD# signal is used to request the PCI bus while the PHLDA# signal is used to acknowledge the request. A state-machine is used to recognize whether a flush request, bus request, or memory request is being made.
In order to perform arbitration of the expansion bus bridge requests, the arbitrator in the host bridge which uses a two-signal protocol described above must be able to process the requests from the expansion bus which uses the five-signal protocol described above. One solution is to provide a new expansion bus bridge which uses the two-wire protocol of the host bridge. However, this requires that users who upgrade their CPU subsystem to include the prior art host bridge will also have to upgrade the expansion bus bridge to maintain a compatible protocol.
What is needed is a method to interface the two-signal arbitration and buffer management protocol of the host bridge to the five-signal buffer management protocol of the expansion bus bridge. In addition, it is desirable to make the arbitration and buffer management protocol selectable depending on the expansion bus bridge such that the host bridge may be upgraded without upgrading the expansion bus bridge.